This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures
April 1988 (vol. 37 no. 4)
pp. 440-448
ASCII Text
x 
 
N. Vasanthavada, P.N. Marinos, "Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures," IEEE Transactions on Computers, vol. 37, no. 4, pp. 440-448, April, 1988.
 
 
BibTex
x
 
@article{ 10.1109/12.2188,
author = {N. Vasanthavada and P.N. Marinos},
title = {Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures},
journal ={IEEE Transactions on Computers},
volume = {37},
number = {4},
issn = {0018-9340},
year = {1988},
pages = {440-448},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.2188},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures
IS - 4
SN - 0018-9340
SP440
EP448
EPD - 440-448
A1 - N. Vasanthavada,
A1 - P.N. Marinos,
PY - 1988
KW - synchronisation; fault-tolerant clocks; malicious failures; clock partitions; clock-receiver triggering; phase-detector operating range; averaging rule; simulations; clocks; fault tolerant computing; logic testing; synchronisation.
VL - 37
JA - IEEE Transactions on Computers
ER -
 
The problem of achieving global clock synchronization in fault-tolerant clocks by preventing so-called multiple cliques in the presence of malicious clock failures (i.e. clock failures that are perceived differently by different nonfaulty clocks) is addressed. A solution to the problem, referred to as the averaging rule, is developed, and its use is analytically justified using the notions of c

[1] W. M. Daly, A. L. Hopkins, and J. F. McKenna, "A fault-tolerant digital clocking system," inDig. 3rd Int. Symp. Fault-Tolerant Comput., June 1973, pp. 17-22.
[2] A. W. Holt and J. M. Myers, "An approach to the analysis of clock networks," NASA Tech. Rep., NASA-CR-166028, Nov. 1982.
[3] J. L. W. Kessels, "Two designs of a fault-tolerant clocking system,"IEEE Trans. Comput., vol. C-33, pp. 912-919, Oct. 1984.
[4] C.M. Krishna, K.G. Shin, and R.W. Butler, "Ensuring Fault Tolerance of Phase-Locked Clocks,"IEEE Trans. Computers, Vol. C- 34, No. 8, Aug. 1985, pp. 752-756.
[5] L. Lamport and P.M. Melliar-Smith, "Synchronizing Clocks in the Presence of Faults,"J. ACM, Vol. 32, No. 1, Jan. 1985, pp. 52-78.
[6] MECL Device Data Book, Motorola Inc., 1983, pp. 7.25-7.29.
[7] K.G. Shin and P. Ramanathan, "Clock Synchronization of a Large Multiprocessor System in the Presence of Malicious Faults,"IEEE Trans. Computers, Vol. C-36, No. 1, Jan. 1987, pp. 2-12.
[8] T. B. Smith, "Fault-tolerant clocking system," inDig. 11th Int. Symp. Fault-Tolerant Comput., June 1981, pp. 262-264.
[9] N. Vasanthavada, P. N. Marinos, and G. S. Mersten, "Design and performance evaluation of mutually synchronized fault-tolerant clock systems," inDig. 16th Int. Symp. Fault-Tolerant Comput., July 1986, pp. 206-211.
[10] N. Vasanthavada, P. N. Marinos, and G. S. Mersten, "A study of fault-tolerant clock systems in the presence of malicious multiple-module faults," inDig. Int. Conf. Comput. Design, Oct. 1986, pp. 516-521.
[11] N. Vasanthavada, "Design and performance verification of mutually synchronized fault-tolerant clocks," Ph.D. dissertation, Dep. Elec. Eng., Duke Univ., Dec. 1986.

Index Terms:
synchronisation; fault-tolerant clocks; malicious failures; clock partitions; clock-receiver triggering; phase-detector operating range; averaging rule; simulations; clocks; fault tolerant computing; logic testing; synchronisation.
Citation:
N. Vasanthavada, P.N. Marinos, "Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures," IEEE Transactions on Computers, vol. 37, no. 4, pp. 440-448, April 1988, doi:10.1109/12.2188
Usage of this product signifies your acceptance of the Terms of Use.