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Issue No.04 - April (1988 vol.37)
pp: 398-405
ABSTRACT
A description is given of the multicomputer architecture for fault tolerance (MAFT), a distributed system designed to provide extremely reliable computation in real-time control systems. MAFT is based on the physical and functional partitioning of executive functions from applications functions. The implementation of the executive functions in a special-purpose hardware processor allows the fau
INDEX TERMS
MAFT architecture; distributed fault tolerance; multicomputer architecture for fault tolerance; real-time control systems; functional partitioning; special-purpose hardware processor; application programs; Byzantine agreement; approximate agreement algorithms; computer architecture; distributed processing; fault tolerant computing.
CITATION
R.M. Keichafer, C.J. Walter, A.M. Finn, P.M. Thambidurai, "The MAFT Architecture for Distributed Fault Tolerance", IEEE Transactions on Computers, vol.37, no. 4, pp. 398-405, April 1988, doi:10.1109/12.2183
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