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A Transition Sequence Generator for RAM Fault Detection
March 1988 (vol. 37 no. 3)
pp. 362-368
In verification of n-bit CMOS memories it is usual to supply a test address sequence having n2/sup /n transitions, one for each ordered pair of n-bit words which differ in a single bit. From an inductive definition of a sequence with these properties, a succession of algorithms yielding the logic circuit of a next-state generator for the sequence is developed. Proving these algorithms equivalen

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Index Terms:
transition sequence generator; RAM fault detection; n-bit CMOS memories; test address sequence; ordered pair; logic circuit; next-state generator; CMOS integrated circuits; integrated circuit testing; integrated memory circuits; random-access storage.
Citation:
E. Regener, "A Transition Sequence Generator for RAM Fault Detection," IEEE Transactions on Computers, vol. 37, no. 3, pp. 362-368, March 1988, doi:10.1109/12.2175
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