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The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI
March 1988 (vol. 37 no. 3)
pp. 329-338
A synthesis method for designing highly parallel algorithms in VLSI is presented. To illustrate the method, the familiar long multiplication algorithm for binary numbers is used. This algorithm is specified in the language Crystal, a very-high-level language for parallel processing. A total of 18 designs are derived from this specification. Each is optimal within its own class, which is charact

[1] P. R. Cappello and K. Steiglitz, "Unifying VLSI array designs with geometric transformations," inProc. IEEE Int. Conf. Parallel Processing, 1983.
[2] M. C. Chen, "Space-time algorithms: Semantics and methodology," Ph.D. dissertation, California Instit. Technol., May 1983.
[3] M. C. Chen, "The generation of a class of multipliers: A synthesis approach to the design of highly parallel algorithms in VLSI," inProc. IEEE Int. Conf. Comput. Design: VLSI Cornput., Oct. 1985, pp. 116- 121.
[4] M. Chen, "A design methodology for synthesizing parallel algorithms and architectures,"J. Parallel Distributed Comput., pp. 461-491, Dec. 1986.
[5] R. Karp, R. Miller, and S. Winograd, "The Organization of Computations for Uniform Recurrence Equations,"J. ACM, Vol. 14, No. 3, 1967, pp. 563-590.
[6] H. T. Kung, "Why systolic architecture?,"IEEE Computer, pp. 37- 46, Jan. 1982.
[7] H. T. Kung and C. E. Leiserson, "Algorithms for VLSI processor arrays," inIntroduction to VLSI Systems, Mead and Conway, Eds. Reading, MA: Addison-Wesley, 1980.
[8] J. Li, M. C. Chen, and M. F. Young, "Design of systolic algorithms for large scale multiprocessors," Tech. Rep. 513, Yale Univ., Feb. 1987.
[9] G.-J. Li and B. W. Wah, "The design of optimal systolic arrays,"IEEE Trans. Comput., vol. C-34, pp. 66-77, Jan. 1985.
[10] T. Z. Lin and C. A. Mead, "The application of group theory in classifying systolic arrays," Display File 5006, Caltech, Mar. 1982.
[11] R. F. Lyon, "A bit-serial VLSI architectural methodology for signal processing,"IEEE Trans. Commun., Apr. 1976.
[12] Z. Manna,Mathematical Theory of Computation. New York: McGraw-Hill, 1974.
[13] C. Mead and J. Wawrzynek, "A new discipline for CMOS design: An architecture for sound synthesis," inProc. 1985 Chapel Hill Conf. VLSI, H. Fuchs, Ed. Computer Science Press, May 1985.
[14] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[15] W. L. Miranker and A. Winkler, "Spacetime representations of computational structures,"Computing, vol. 32, pp. 93-114, 1984.
[16] D. I. Moldovan, "On the design of algorithms for VLSI systolic arrays,"IEEE Trans. Comput., 1983.
[17] D. I. Moldovan, "ADVIS: A software package for the design of systolic arrays," inProc. ICCD, 1984.
[18] P. Quinton, "Automatic synthesis of systolic arrays from uniform recurrent equations," inProc. 11th Annu. Symp. Comput. Architecture, 1984, pp. 208-214.
[19] D. S. Scott and C. Strachey," Toward a mathematical semantics for computer languages," inProc. Symp. Comput. Automata, J. Fox, Ed. New York: Polytechnic Institute of Brooklyn Press, 1971, pp. 19-46.
[20] D. A. Turner, "Recursion equations as a programming language," inFunctional Programming and Its Applications, Cambridge, MA: Cambridge Univ. Press, 1982, pp. 1-28.

Index Terms:
highly parallel algorithms synthesis; multipliers; VLSI; long multiplication algorithm; binary numbers; Crystal; digital arithmetic; parallel algorithms; parallel architectures; VLSI.
Citation:
M.C. Chen, "The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI," IEEE Transactions on Computers, vol. 37, no. 3, pp. 329-338, March 1988, doi:10.1109/12.2170
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