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Issue No.03 - March (1988 vol.37)
pp: 291-300
ABSTRACT
In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. Here, the capability of random patterns to detect slow paths in combinational logic is analyzed. Formulas that r
INDEX TERMS
random pattern testability; delay faults; combinational logic networks; latches; system clocks; combinatorial circuits; logic testing.
CITATION
J. Savir, W.H. McAnney, "Random Pattern Testability of Delay Faults", IEEE Transactions on Computers, vol.37, no. 3, pp. 291-300, March 1988, doi:10.1109/12.2166
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