Issue No.03 - March (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.2165
The design of a special-purpose CMOS processor for digital signal processing is described. A high degree of processing concurrency is achieved through the use of two modified pipelined architectures in parallel. Each pipeline section is connected to a bus for maximum flexibility in accessing any stage in the pipeline. Each pipeline section can be dynamically configured under microprogram contro
multiple-access pipeline architecture; digital signal processing; CMOS processor; processing concurrency; microprogram control; floating-point data; arithmetic logic unit; computerised signal processing; digital arithmetic; parallel architectures.
B.C. McKinney, F. El Guibaly, "A Multiple-Access Pipeline Architecture for Digital Signal Processing", IEEE Transactions on Computers, vol.37, no. 3, pp. 283-290, March 1988, doi:10.1109/12.2165