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A Single Chip Parallel Multiplier by MOS Technology
March 1988 (vol. 37 no. 3)
pp. 274-282
ASCII Text
x 
 
S. Nakamura, K.-Y. Chu, "A Single Chip Parallel Multiplier by MOS Technology," IEEE Transactions on Computers, vol. 37, no. 3, pp. 274-282, March, 1988.
 
 
BibTex
x
 
@article{ 10.1109/12.2164,
author = {S. Nakamura and K.-Y. Chu},
title = {A Single Chip Parallel Multiplier by MOS Technology},
journal ={IEEE Transactions on Computers},
volume = {37},
number = {3},
issn = {0018-9340},
year = {1988},
pages = {274-282},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.2164},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A Single Chip Parallel Multiplier by MOS Technology
IS - 3
SN - 0018-9340
SP274
EP282
EPD - 274-282
A1 - S. Nakamura,
A1 - K.-Y. Chu,
PY - 1988
KW - single chip parallel multiplier; MOS technology; five-counter cell; design optimization; logic design level; full adder cell design; field effect integrated circuits; integrated logic circuits; logic design; multiplying circuits.
VL - 37
JA - IEEE Transactions on Computers
ER -
 
A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication

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Index Terms:
single chip parallel multiplier; MOS technology; five-counter cell; design optimization; logic design level; full adder cell design; field effect integrated circuits; integrated logic circuits; logic design; multiplying circuits.
Citation:
S. Nakamura, K.-Y. Chu, "A Single Chip Parallel Multiplier by MOS Technology," IEEE Transactions on Computers, vol. 37, no. 3, pp. 274-282, March 1988, doi:10.1109/12.2164
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