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A 20 Bit Logarithmic Number System Processor
February 1988 (vol. 37 no. 2)
pp. 190-200
The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA

[1] K. Hwang,Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979.
[2] F. Taylor, "Residue arithmetic: A tutorial with examples,"IEEE Computer, May 1984.
[3] N. G. Kingsbury and P. J. W. Rayner, "Digital filtering using logarithmic arithmetic,"Electron. Lett., Jan. 28, 1971.
[4] T. C. Chen, "Automatic computation of exponentials, logs, ratios, and square roots,"IBM J. Res Develop., pp. 380-388, July 1972.
[5] E. E. Swartzlander and A. G. Alexpoulous, "The signed logarithm number system,"IEEE Trans. Comput., Dec. 1975.
[6] S. C. Lee and A. D. Edgar, "The focus number system,"IEEE Trans. Comput., Nov. 1977.
[7] T. Kurokawa, J. A. Payne, and S. C. Lee, "Error analysis of recursive digital filters implemented with logarithmic number systems,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-28, pp. 706-715, Dec. 1980.
[8] F. J. Taylor, "An extended precision logarithmic number system,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-31, pp. 231-233, Feb. 1983.
[9] E. E. Swarzlanderet al., "Sign/logarithm arithmetic for FFT implementation,"IEEE Trans. Comput., June 1983.
[10] M. H. Etzeh, "Logarithmic addition for digital signal processing applications," inProc. 1983 IEEE Int. Symp. Comput. Sci., 1983.
[11] V. P. Shenoyet al., "Error analysis of a-LMS adaptive digital filter implemented with a logarithmic number system," inProc. ICASSP 84, San Diego, CA, 1984.
[12] F. J. Taylor, "A hybrid floating-point logarithmic number system processor,"IEEE Trans. Circuits Syst., vol. CAS-32, pp. 92-95, Jan. 1985.
[13] T. Stouraitis, S. Natarajan, and F. Taylor, "A reconfigurable systolic primitive processor for signal processing," inProc. IEEE Symp. Acoust. Speech. Signal Processing, 1985.
[14] J. H. Langet al., "Integrated-circuit logarithmic units,"IEEE Trans. Comput., May 1985.
[15] M. L. Frey and F. J. Taylor, "A table reduction technique for logarithmically architected digital filters,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-33, pp. 718-719, June 1985.
[16] H.-Y. Lo and Y. Aoki, "Generation of a precise binary logarithm with difference grouping programmable logic array,"IEEE Trans. Comput., vol. C-34, pp. 681-691, Aug. 1985.

Index Terms:
logarithmic number system processor; architecture; arithmetic processor; table lookup; partitioned memory; ROM; PLA; performance evaluation; integrated Schottky logic; 20 bit; computer architecture; digital arithmetic; field effect integrated circuits; microprocessor chips; performance evaluation; satellite computers; table lookup.
F.J. Taylor, R. Gill, J. Joseph, J. Radke, "A 20 Bit Logarithmic Number System Processor," IEEE Transactions on Computers, vol. 37, no. 2, pp. 190-200, Feb. 1988, doi:10.1109/12.2148
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