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J.C. Harden, N.R. Stader, II, "Architectural Yield Optimization for WSI," IEEE Transactions on Computers, vol. 37, no. 1, pp. 88110, January, 1988.  
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@article{ 10.1109/12.75138, author = {J.C. Harden and N.R. Stader, II}, title = {Architectural Yield Optimization for WSI}, journal ={IEEE Transactions on Computers}, volume = {37}, number = {1}, issn = {00189340}, year = {1988}, pages = {88110}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.75138}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Architectural Yield Optimization for WSI IS  1 SN  00189340 SP88 EP110 EPD  88110 A1  J.C. Harden, A1  N.R. Stader, II, PY  1988 KW  architectural yield optimisation; waferscale integration; integrated circuit yield modeling; computing structures; circuit reliability; computer architecture; failure analysis; fault tolerant computing; redundancy; VLSI. VL  37 JA  IEEE Transactions on Computers ER   
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