Issue No.01 - January (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.75138
A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale
architectural yield optimisation; wafer-scale integration; integrated circuit yield modeling; computing structures; circuit reliability; computer architecture; failure analysis; fault tolerant computing; redundancy; VLSI.
J.C. Harden, N.R. Stader, II, "Architectural Yield Optimization for WSI", IEEE Transactions on Computers, vol.37, no. 1, pp. 88-110, January 1988, doi:10.1109/12.75138