Issue No.01 - January (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.75140
A design method using both logical optimization and optimized topological arrangements is described. Starting from a minimized Boolean function, a synthesis of an optimized well-structured network is obtained. The most original aspect of this approach is a transistor merging procedure leading to a nonseries-parallel network while maintaining a systematic layout. An extension to the synthesis of
optimised MOS cell layout; logical optimization; optimized topological arrangements; minimized Boolean function; well-structured network; transistor merging procedure; nonseries-parallel network; circuit layout CAD; field effect integrated circuits; logic design; minimisation of switching nets.
G. Thuau, G. Saucier, "Optimized Layout of MOS Cells", IEEE Transactions on Computers, vol.37, no. 1, pp. 79-87, January 1988, doi:10.1109/12.75140