|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| M. Dubois, "Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses," IEEE Transactions on Computers, vol. 37, no. 1, pp. 58-70, January, 1988. | |||
| BibTex | x | ||
| @article{ 10.1109/12.75139, author = {M. Dubois}, title = {Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses}, journal ={IEEE Transactions on Computers}, volume = {37}, number = {1}, issn = {0018-9340}, year = {1988}, pages = {58-70}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.75139}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses IS - 1 SN - 0018-9340 SP58 EP70 EPD - 58-70 A1 - M. Dubois, PY - 1988 KW - shared interleaved memory; cache-based multiprocessors; multiple buses; performance; general-purpose computing; multitasking; throughput; private cache; dynamic instruction mix statistics; buffer storage; multiprocessing systems; performance evaluation. VL - 37 JA - IEEE Transactions on Computers ER - | |||
[1] L. Adams and J. Ortega, "A multi-color SOR method for parallel computations," inProc. 1982 Conf. Parallel Processing, Aug. 1982.
[2] G. R. Andrews and F. B. Schneider, "Concepts and notations for concurrent programming,"ACM Comput. Surveys, vol. 15, no. 1, pp. 3-43, Mar. 1983.
[3] J. Archibald and J. L. Baer, "Cache-coherence protocols: Evaluation using a multiprocessor simulation model,"ACM Trans. Comput. Syst., vol. 4, no. 4, pp. 273-298, Nov. 1986.
[4] F. A. Briggs and M. Dubois, "Effectiveness of private caches in multiprocessor systems with parallel-pipelined memories,"IEEE Trans. Comput., vol. C-32, pp. 48-59, Jan. 1983.
[5] D. Del Corso, H. Kirrman, and J. D. Nicoud,Microcomputer Buses and Links. New York: Academic, 1986.
[6] J. Deminet, "Experience with multiprocessor algorithms,"IEEE Trans. Comput., vol. C-31, Apr. 1982.
[7] M. Dubois and F. A. Briggs, "Effects of cache coherency in multiprocessors,"IEEE Trans. Comput., vol. C-31, pp. 1083-1099, Nov. 1982.
[8] M. Dubois, "Performance of SOR algorithms in multiprocessors," inProc. Second Int. Conf. Supercomput., May 1987.
[9] S. J. Frank, "Tightly-coupled multiprocessor system speeds memory-access time,"Electronics, pp. 164-169, Jan. 1984.
[10] E. F. Gehringeret al., "The Cm*testbed,"IEEE Computer, Oct. 1982.
[11] C. M. Hoogendorn, "A general model for memory interference in multiprocessors,"IEEE Trans. Comput., vol. C-26, pp. 998-1005, Oct. 1977.
[12] A.K. Jones and P. Schwarz, "Experience Using Multiprocessor Systems--A Status Report,"Computing Surveys, June 1980, pp. 121-165.
[13] P. M. Kogge,The Architecture of Pipelined Computers. New York: McGraw-Hill, 1981.
[14] H. T. Kung, "Synchronized and asynchronous parallel algorithms for multiprocessors," inAlgorithms and Complexity: New Directions and Recent Results, J. F. Traub, Ed. New York: Academic, 1976.
[15] D. Kroft, "Lockup-free instruction fetch/prefetch cache organization," inProc. 8th Annu. Symp. Comput. Architecture, June 1981, pp. 81-87.
[16] W. Mayberry, "Cache boosts multiprocessor performance,"Comput. Design, Nov. 1984.
[17] T. N. Mudge and H. B. Al-Sadoun, "Memory interference models with variable connection time,"IEEE Trans. Comput., vol. C-33, Nov. 1984.
[18] M. S. Papamarcos and J. H. Patel, "A low-overhead coherence solution for multiprocessors with private cache memories," inProc. 11th Int. Symp. Comput. Architecture, June 1984, pp. 348-354.
[19] J. H. Patel, "Analysis of multiprocessors with private cache memories,"IEEE Trans. Comput., vol. C-31, pp. 296-304, Apr. 1982.
[20] A. Smith, "Cache Memories,"Computing Surveys, Vol. 14, No. 3, Sept. 1982, pp. 473- 530.
[21] K. J. Thurberet al., "A systematic approach to the design of digital bussing structures," inProc. FJCC, 1972, pp. 719-740.
[22] VAX 780 Hardware Handbook, DEC., 1978, section on SBI backplane bus.
[23] D. Vrsalovicet al., "The influence of parallel decomposition strategies on the performance of multiprocessor systems," inProc. 1985 Comput. Architecture Symp.
[24] M. V. Wilkes, "Size, power, and speed," Keynote Address, inProc. 10th Int. Symp. Comput. Architecture, May 1983, pp. 2-4.
[25] D. Young,Iterative Solution of Large Linear Systems. New York: Academic, 1971.

