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Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses
January 1988 (vol. 37 no. 1)
pp. 58-70
The performance of cache-based multiprocessors for general-purpose computing and for multitasking is analyzed with simple throughput models. A private cache is associated with each processor, and multiple buses connect the processors to the shared, interleaved memory. Simple models based on dynamic instruction mix statistics are introduced to evaluate upper bounds on the throughput when indepen

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Index Terms:
shared interleaved memory; cache-based multiprocessors; multiple buses; performance; general-purpose computing; multitasking; throughput; private cache; dynamic instruction mix statistics; buffer storage; multiprocessing systems; performance evaluation.
Citation:
M. Dubois, "Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses," IEEE Transactions on Computers, vol. 37, no. 1, pp. 58-70, Jan. 1988, doi:10.1109/12.75139
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