This Article 
 Bibliographic References 
 Add to: 
Multipipeline Networking for Compound Vector Processing
January 1988 (vol. 37 no. 1)
pp. 33-47
An efficient vector-processing technique is proposed; it is based on a novel concept of multipipeline networking, which is generalized from the techniques of pipeline chaining and systolization. The authors also present the design principles of pipeline nets and provide programming, compiling and run-time techniques for converting scientific programs into pipeline net implementations. Performan

[1] W. B. Ackerman, "Data flow languages,"IEEE Computer, vol. 15, pp. 15-25, Feb. 1982.
[2] A. K. Agrawala and T. G. Rauscher,Foundations of Microprogramming. New York: Academic, 1976, pp. 73-75.
[3] A. V. Aho, J. E. Hopcroft, and J. D. Ullman,The Design and Analysis of Computer Algorithms. Menlo Park, CA: Addison-Wesley, 1974.
[4] Annaratone et al., "Warp Architecture and Implementation,"Proc. 13th Ann. Symp. Computer Architecture, June 1986, pp. 346- 356.
[5] C. Y. Chin and K. Hwang, "Packet switching networks for multiprocessors and data flow computers,"IEEE Trans. Comput., vol. C-33, pp. 991-1003, Nov. 1984.
[6] W. Crowther, J. Goodhue, E. Starr, R. Thomas, W. Milliken, and T. Blackadar, "Performance measurements on a 128-node butterfly parallel processor," inProc. 1985 Int. Conf. Parallel Processing, Aug. 1985, pp. 531-540.
[7] E. S. Davidson, "Scheduling for pipelined processors," inProc. 7th Hawaii Conf. Syst. Sci., 1974, pp. 58-60.
[8] J. B. Dennis and G. R. Gao, "Maximum pipelining of array operations on static data flow machine," inProc. 1983 Int. Conf. Parallel Processing, Aug. 1983, pp. 331-334.
[9] M. W. Ferrante, "Cyberplus and Map V interprocessor communications for parallel and array processor systems,"Multiprocessors Array Processors, Simulation Councils, Inc., San Diego, CA, Jan. 1987, pp. 45-54.
[10] D. D. Gajski, "An algorithm for solving linear recurrence systems on parallel and pipelined machines,"IEEE Trans. Comput., vol. C-30, pp. 190-205, Mar. 1981.
[11] R. L. Graham, "Bounds on multiprocessing timing anomalies,"SIAM J. Appl. Math., vol. 17, pp. 416-429, 1969.
[12] S. Hawkinson, "The FPS T Series: A parallel vector super computer,"Multiprocessors Array Processors, Simulation Councils, Inc., San Diego, CA, Jan. 1987, pp. 147-156.
[13] R. W. Hockney and C. R. Jesshope,Parallel Computers. Bristal: Adam Hilger, 1981, pp. 51-64.
[14] F. H. Hsu, H. T. Kung, T. Nishizawa, and A. Sussman, "LINC: The link and interconnection chip," Dep. Comput. Sci., Carnegie-Mellon Univ., 1984.
[15] K. Hwang and Y. H. Cheng, "Partitioned matrix algorithms for VLSI arithmetic systems,"IEEE Trans. Comput., vol. C-31, pp. 1215- 1224, Dec. 1982.
[16] K. Hwang and F. A. Briggs,Computer Architecture and Parallel Processing. New York: McGraw-Hill, 1984.
[17] K. Hwang and Z. Xu, "Multiprocessor for evaluating compound arithmetic functions," inProc. 7th Symp. Comput. Arithmetic, June 1985, pp. 266-275.
[18] K. Hwang, Z. Xu, and A. Louri, "Remps: An electro-optical supercomputer for parallel solution of PDE problems," inProc. Second Int. Conf. Supercomput., May 1987.
[19] K. Hwang, H. C. Wang, and Z. Xu, "Evaluating elementary functions with Chebyshev polynomials on pipeline nets," inProc. Eighth Symp. Comput. Arithmetic, June 1987.
[20] P. M. Kogge,The Architecture of Pipelined Computers. New York: McGraw-Hill, 1981, pp. 57-66.
[21] H. T. Kung and C. E. Leiserson, "Systolic arrays (for VLSI),"Sparse Matrix Proc., pp. 32-63, 1978.
[22] H. T. Kung and M. S. Lam, "Wafer-scale integration and two-level pipelined implementations of systolic arrays,"J. Parallel Distributed Processing, vol. 1, Aug. 1984.
[23] S. Y. Kung, "On supercomputing with systolic/wavefront array processors,"Proc. IEEE, vol. 72, pp. 867-884, July 1984.
[24] C. E. Leiserson and J. B. Saxe, "Optimizing synchronous systems,"J. VLSI Comput. Syst., vol. 1, pp. 41-68, Spring 1983.
[25] W. T. Lin and C. Y. Ho, "A new FFT mapping algorithm for reducing the traffic in a processor array," inVLSI Signal Processing II, Kung, Owen, and Nash, Eds. New York: IEEE Press, 1986, pp. 328-336.
[26] W. T. Lin and C. Y. Chin, "A reconfigurable array using LINC chip," inSystolic Arrays, Moore, McCabe, and Urguhart, Eds. Bristal: Adam Hilger, 1987, pp. 313-320.
[27] L. M. Ni and K. Hwang, "Vector reduction techniques for arithmetic systems,"IEEE Trans. Comput., vol. C-34, pp. 404-411, May 1985.
[28] Cray Research, Inc.,The Cray X-MP Series of Computer Systems, 1984.
[29] J. P. Riganati and P. B. Schneck, "Supercomputing,"IEEE Comput. Mag., vol. 17, no. 10, pp. 97-113, Oct. 1984.
[30] A. A. Sawchuk, B. K. Jenkins, C. S. Raghavendra, and A. Varma, "Optical interconnection networks," inProc. Int. Conf. Parallel Processing, Aug. 1985, pp. 388-392.
[31] L. Snyder, "Introduction to the configurable, highly parallel computer,"IEEE Computer, vol. 15, pp. 47-64, Jan. 1982.
[32] T. Watanabe, "Architecture of supercomputers--NEC supercomputer SX system,"NEC Res. Develop., no. 73, April 1984.
[33] X. Xu and K. Hwang, "Molecule: A language construct for layered development of parallel programs,"IEEE Trans. Software Eng., 1988, to be published.
[34] Z. Xu, K. Hwang, and B. K. Jenkins, "Opcom: An architecture for optical computing based on pipeline networking," inProc. Twentieth Annu. Hawaii Int. Conf. Syst. Sci., vol. 1, Jan. 1987, pp. 147-156.

Index Terms:
performance analysis; compilation; compound vector processing; vector-processing; multipipeline networking; pipeline chaining; systolization; pipeline nets; programming; run-time techniques; scientific programs; Livermore loops; parallel architectures; parallel programming; performance evaluation; pipeline processing; program compilers.
K. Hwang, Z. Xu, "Multipipeline Networking for Compound Vector Processing," IEEE Transactions on Computers, vol. 37, no. 1, pp. 33-47, Jan. 1988, doi:10.1109/12.75149
Usage of this product signifies your acceptance of the Terms of Use.