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Issue No.10 - October (1987 vol.36)
pp: 1243-1247
null I-Chen wu , Department of Computer Science, Carnegie-Mellon University
ABSTRACT
Based on the modified Booth's algorithm, a fast 1-D serial- parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2 cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n = N) multiplier and an m-bit multiplicand is equal to n + m - 1, and independent of the circuit size N.
INDEX TERMS
VLSI, Countercurrent data flow pattern, five-level multiplexer, five-level recorder, modified Booth's Algorithm, systolic multilier, two's complement
CITATION
null I-Chen wu, "A Fast 1-D Serial-Parallel Systolic Multiplier", IEEE Transactions on Computers, vol.36, no. 10, pp. 1243-1247, October 1987, doi:10.1109/TC.1987.1676865
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