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Issue No.05 - May (1987 vol.36)
pp: 640-644
C.N. Purdy , Department of Computer Science, University of Cincinnati
ABSTRACT
A binary algorithm for division of an (M + N)-bit integer by an N-bit integer is presented. The algorithm produces the (M + 1)-bit quotient and the N-bit remainder in time O(M + N). Two hardware implementations, one using combinational logic in cellular arrays, and one employing systolic arrays, are given. These implementations are designed for modularity and regularity, and thus are suitable for VLSI systems. An important property of these implementations is that decisions are based on only one bit of the operands. Thus, fan-in and length of connecting wires are bounded independently of operand size. In addition, the systolic implementation has area O + N), which is the best possible.
INDEX TERMS
VLSI, Binary division, cellular array, chip layout, circuit design, combinational logic, hardware divider, integer arithmetic, logic design, systolic array
CITATION
C.N. Purdy, G.B. Purdy, "Integer Division in Linear Time with Bounded Fan-In", IEEE Transactions on Computers, vol.36, no. 5, pp. 640-644, May 1987, doi:10.1109/TC.1987.1676952
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