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May 1987 (vol. 36 no. 5)
pp. 529-537
R. Chillarege, IBM Thomas J. Watson Research Center
This paper demonstrates a practical methodology for the study of error latency under a real workload. The method is illustrated with sampled data on the physical memory activity, gathered by hardware instrumentation on a VAX 11/780 during the normal workload cycle of the installation. These data are used to simulate fault occurrence and to reconstruct the error discovery process in the system. The technique provides a means to study the system under different workloads and for multiple days. An approach to determine the percentage of undiscovered errors is also developed and a verification of the entire methodology is performed. This study finds that the mean error latency, in the memory containing the operating system, varies by a factor of 10 to 1 (in hours) between the low and high workloads. It is found that of all errors occurring within a day, 70 percent are detected in the same day, 82 percent within the following day, and 91 percent within the third day. The increase in failure rate due to latency is not so much a function of remaining errors but is dependent on whether or not there is a latent error.
Index Terms:
experimental measurement analysis, Error latency and workload analysis, failure
Citation:
R. Chillarege, R.K. Iyer, "Measurement-Based Analysis of Error Latency," IEEE Transactions on Computers, vol. 36, no. 5, pp. 529-537, May 1987, doi:10.1109/TC.1987.1676937
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