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Evaluation of On-Chip Static Interconnection Networks
March 1987 (vol. 36 no. 3)
pp. 365-369
P. Mazumder, Coordinated Science Laboratory, University of Illinois
This correspondence evaluates three types of static interconnection networks for VLSI implementation. The criteria of evaluation have been selected from three orthogonal aspects-physical (chip area and dissipation), computational speed (message delay and message density) and cost (chip yield, operational reliability and layout cost). The main feature of this paper is to augment the selection criteria for the interconnection networks from the classical AT2 metric and to provide results pertaining to realistic VLSI implementation.
Index Terms:
VLSI implementation, Binary tree, cube connected cycles, static interconnection networks, two-dimensional meshes
Citation:
P. Mazumder, "Evaluation of On-Chip Static Interconnection Networks," IEEE Transactions on Computers, vol. 36, no. 3, pp. 365-369, March 1987, doi:10.1109/TC.1987.1676910
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