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Pseudorandom Testing
March 1987 (vol. 36 no. 3)
pp. 332-343
K.D. Wagner, EDS VLSI Design Rules Control Department, IBM
Algorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile.
Index Terms:
test length, Detectability profile, fault coverage, pseudorandom testing, random testing, test confidence, test generation
Citation:
K.D. Wagner, C.K. Chin, E.J. McCluskey, "Pseudorandom Testing," IEEE Transactions on Computers, vol. 36, no. 3, pp. 332-343, March 1987, doi:10.1109/TC.1987.1676905
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