Issue No.03 - March (1987 vol.36)
D.H. Bailey , Numerical Aerodynamic Simulation Systems Division, NASA Ames Research Center
A number of recent vector supercomputer designs have featured main memories with very large capacities, and presumably even larger memories are planned for future generations. While the memory chips used in these computers can store much larger amounts of data than before, their operation speeds are rather slow when compared to the significantly faster CPU (central processing unit) circuitry in new supercomputer designs. A consequence of this speed disparity between CPU's and main memory is that memory access times and memory bank reservation times (as measured in CPU ticks) are sharply increased from previous generations.
vector computers, Interleaved memories, Markov chains, memory bank contention, supercomputers
D.H. Bailey, "Vector Computer Memory Bank Contention", IEEE Transactions on Computers, vol.36, no. 3, pp. 293-298, March 1987, doi:10.1109/TC.1987.1676901