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On the Time-Bandwidth Proof in VLSI Complexity
February 1987 (vol. 36 no. 2)
pp. 239-240
Y.S. Abu-Mostafa, Departments of Electrical Engineering and Computer Science, California Institute of Technology
A subtle fallacy in the original proof [1] that the computation time T is lowerbounded by a factor inversely proportional to the minimum bisection width of a VLSI chip is pointed out. A corrected version of the proof using the idea of conditionally self-delimiting messages is given.
Index Terms:
VLSI complexity, Bisected graph, computation time, information theory, lower bounds, self-delimiting
Citation:
Y.S. Abu-Mostafa, "On the Time-Bandwidth Proof in VLSI Complexity," IEEE Transactions on Computers, vol. 36, no. 2, pp. 239-240, Feb. 1987, doi:10.1109/TC.1987.1676888
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