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On the Time-Bandwidth Proof in VLSI Complexity
February 1987 (vol. 36 no. 2)
pp. 239-240
| ASCII Text | x | ||
| Y.S. Abu-Mostafa, "On the Time-Bandwidth Proof in VLSI Complexity," IEEE Transactions on Computers, vol. 36, no. 2, pp. 239-240, February, 1987. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1987.1676888, author = {Y.S. Abu-Mostafa}, title = {On the Time-Bandwidth Proof in VLSI Complexity}, journal ={IEEE Transactions on Computers}, volume = {36}, number = {2}, issn = {0018-9340}, year = {1987}, pages = {239-240}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1987.1676888}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - On the Time-Bandwidth Proof in VLSI Complexity IS - 2 SN - 0018-9340 SP239 EP240 EPD - 239-240 A1 - Y.S. Abu-Mostafa, PY - 1987 KW - VLSI complexity KW - Bisected graph KW - computation time KW - information theory KW - lower bounds KW - self-delimiting VL - 36 JA - IEEE Transactions on Computers ER - | |||
A subtle fallacy in the original proof [1] that the computation time T is lowerbounded by a factor inversely proportional to the minimum bisection width of a VLSI chip is pointed out. A corrected version of the proof using the idea of conditionally self-delimiting messages is given.
Index Terms:
VLSI complexity, Bisected graph, computation time, information theory, lower bounds, self-delimiting
Citation:
Y.S. Abu-Mostafa, "On the Time-Bandwidth Proof in VLSI Complexity," IEEE Transactions on Computers, vol. 36, no. 2, pp. 239-240, Feb. 1987, doi:10.1109/TC.1987.1676888
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