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February 1987 (vol. 36 no. 2)
pp. 215-226
M. Karpovsky, College of Engineering, Boston University
In this correspondence we present a design technique for implementation of systems of Boolean functions in the form of multilevel AND-OR networks. We show that for a given system of Boolean functions, the transition from the traditional two-level AND-OR implementation to multilevel AND-OR implementations results in considerable savings in gate counts and delays. We discuss gate-array implementations of these multilevel networks and their space and time complexities. Experimental data for 11 different components of peripheral control units for VAX computers indicate that the transition from the two-level implementations to multilevel implementations results in average savings of about 40 percent in gate counts, of about 25 percent in required silicon areas and of about 25 percent in delays, which illustrate a good potential of the proposed techniques for design of cost-efficient gate arrays.
Index Terms:
time and space complexity of gate arrays, AND-OR implementations of systems of Boolean functions, delays, gate arrays, gate counts, multilevel logical networks
Citation:
M. Karpovsky, "Multilevel Logical Networks," IEEE Transactions on Computers, vol. 36, no. 2, pp. 215-226, Feb. 1987, doi:10.1109/TC.1987.1676884
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