Issue No.02 - February (1987 vol.36)
S.M. Reddy , Department of Electrical and Computer Engineering, University of Iowa
Programmable logic arrays (PLA's) are extensively used to realize area efficient combinational logic circuits. As the size of the PLA's increases, a cost-effective way to test them is to realize testable PLA's. In this paper a new approach to the design of testable PLA's is presented. The proposed method leads to testable PLA's with minimal area penalty and small number of tests that can be obtained as a by-product of the synthesis procedure, or can be directly obtained from the personality of the PLA's, thus simplifying the test derivation step. Results of an experiment involving 56 PLA's, to compare the test set sizes of differenit testable PLA designs (including the design proposed here) as well as the size of tests derived to detect single faults by algorithmic procedures are also reported.
testing, Fault detection, multiple faults, programmable logic array (PLA), testable design
S.M. Reddy, "A New Approach to the Design of Testable PLA's", IEEE Transactions on Computers, vol.36, no. 2, pp. 201-211, February 1987, doi:10.1109/TC.1987.1676882