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Issue No.11 - November (1986 vol.35)
pp: 1000-1004
B.P. Sinha , Electronics Unit, Indian Statistical Institute
ABSTRACT
In this correspondence we develop a parallel algorithm to compute the all-pairs shortest paths and the diameter of a given graph. Next, this algorithm is mapped into a suitable VLSI systolic architecture and the performance of this proposed VLSI implementation is evaluated.
INDEX TERMS
VLSI architecture, Diameter, parallel algorithms, pipelining, shortest paths
CITATION
B.P. Sinha, B.B. Bhattacharya, S. Ghose, P.K. Srimani, "A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation", IEEE Transactions on Computers, vol.35, no. 11, pp. 1000-1004, November 1986, doi:10.1109/TC.1986.1676702
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