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Dual Systolic Architectures for VLSI Digital Signal Processing Systems
October 1986 (vol. 35 no. 10)
pp. 916-923
G.E. Bridges, Department of Electrical Engineering, University of Manitoba
This correspondence presents a linear systolic array for the implementation pf digital signal processing systems based upon matrix- vector multiplication algorithms where the matrix elements can be computed from their row and column indexes. Haar, Walsh, and the discrete Fourier transforms are solved using this approach. The method presented enables the n2 matrix elements to be computed in situ directly from the 2n matrix indexes. Thus, performance comparable to known systolic matrix-vector multipliers is achieved using only constant I/O bandwidth, rather than O(n) bandwidth required in the more general case. A generalized method is given for the development of recursively formed matrices and specifically the VLSI implementation of the Haar and Walsh transforms.
Index Terms:
VLSI, Logic design, matrix multiplication algorithms, parallel computation, systolic architectures
G.E. Bridges, W. Pries, R.D. McLeod, M. Yunik, P.G. Gulak, H.C. Card, "Dual Systolic Architectures for VLSI Digital Signal Processing Systems," IEEE Transactions on Computers, vol. 35, no. 10, pp. 916-923, Oct. 1986, doi:10.1109/TC.1986.1676684
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