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Issue No.10 - October (1986 vol.35)
pp: 896-901
T. Rhyne , MCC
ABSTRACT
Bit-sequential algorithms for arithmetic processing are good candidates for VLSI signal processing circuits because of their canonical structure and minimal interconnection requirements. Several recent papers have dealt with algorithms that accept unsigned binary inputs, one bit at a time, least significant bit first, and produce an unsigned binary product in a bit-serial fashion.
INDEX TERMS
VLSI signal processing circuits, Bit-sequential multiplication, Booth's algorithm, carry-save arithmetic, computer arithmetic
CITATION
T. Rhyne, N.R., II Strader, "A Signed Bit-Sequential Multiplier", IEEE Transactions on Computers, vol.35, no. 10, pp. 896-901, October 1986, doi:10.1109/TC.1986.1676680
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