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Issue No.10 - October (1986 vol.35)
pp: 862-870
K. Kinoshita , Department of Information ahd Behavioral Sciences, Faculty of Integrated Arts and Sciences, Hiroshima University
In this paper we study the problem of testing RAM. A new fault model, which encompasses the existing fault models, is proposed. We then propose a scheme of testing faults from the new fault model using built-in testing techniques. We introduce concept of p-hard and determine the complexity of the extra hardware required for built-in self-testing on our hardness scale. A novel approach using microcoded ROM for implementation of built-in testing is also proposed and its complexity is determined.
weight-sensitive faults, Built-in self-testing (BIST), built-in testing (BIT), hardware complexity, pattern-sensitive faults, random- access memory (RAM), stuck-at faults
K. Kinoshita, K.K. Saluja, "Built-In Testing of Memory Using an On-Chip Compact Testing Scheme", IEEE Transactions on Computers, vol.35, no. 10, pp. 862-870, October 1986, doi:10.1109/TC.1986.1676677
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