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Issue No.09 - September (1986 vol.35)
pp: 815-828
R.D. Acosta , Microelectronics and Computer Technology Corporation
ABSTRACT
Processors with multiple functional units, such as CRAY-1, Cyber 205, and FPS 164, have been used for high-end scientific computation tasks. Much effort has been put into increasing the throughput of such systems. One critical consideration in their design is the identification and implementation of a suitable instruction issuing scheme. Existing approaches do not issue enough instructions per machine cycle to fully utilize the functional units and realize the high-performance level achievable with these powerful execution resources.
INDEX TERMS
processor performance enhancement, Dispatch stack, dynamic instruction scheduling, instruction issuing, instruction unit, multiple functional unit processors, multiple instruction dispatching
CITATION
R.D. Acosta, J. Kjelstrup, H.C. Torng, "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors", IEEE Transactions on Computers, vol.35, no. 9, pp. 815-828, September 1986, doi:10.1109/TC.1986.1676841
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