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I.S. Reed, Department of Electrical Engineering, University of Southern California
In this paper a recursive algorithm using the error-trellis decoding technique is developed to decode certain convolutional codes (CC's). An example, illustrating the VLSI architecture of such a decoder, is given for a dual-k CC. It is demonstrated that such a decoder can be realized readily on a single chip with NMOS technology.
Index Terms:
Wyner-Ash code, Convolutional code, error-trellis syndrome decoder, VLSI
Citation:
I.S. Reed, T.K. Truong, J.M. Jensen, null In-Shek Hsu, "The VLSI Design of an Error-Trellis Syndrome Decoder for Certain Convolutional Codes," IEEE Transactions on Computers, vol. 35, no. 9, pp. 781-789, Sept. 1986, doi:10.1109/TC.1986.1676838
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