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Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection
May 1986 (vol. 35 no. 5)
pp. 462-475
V. Ramachandran, Coordinated Science Laboratory, University of Illinois
We present algorithms and time complexity results for MOS switch-level simulation with particular reference to race detection. Under the switching model used in classical (Boolean) switching theory, we derive a linear-time race detection algorithm for switch-level circuits that have no feedback within a clock phase, and have unit fan-out. We show that the problem becomes NP-complete if fan-out of two or more is allowed. We Also relate this result to others that have recently been reported, using a different switching model.
Index Terms:
switch-level simulation, Computer-aided design tools, graph algorithms, linear-time simulation, MOS VLSI, NP-completeness, race detection
Citation:
V. Ramachandran, "Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection," IEEE Transactions on Computers, vol. 35, no. 5, pp. 462-475, May 1986, doi:10.1109/TC.1986.1676789
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