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A Study of Pipelining in Computing Arrays
May 1986 (vol. 35 no. 5)
pp. 431-440
| ASCII Text | x | ||
| H.V. Jagadish, R.G. Mathews, T. Kailath, J.A. Newkirk, "A Study of Pipelining in Computing Arrays," IEEE Transactions on Computers, vol. 35, no. 5, pp. 431-440, May, 1986. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1986.1676785, author = {H.V. Jagadish and R.G. Mathews and T. Kailath and J.A. Newkirk}, title = {A Study of Pipelining in Computing Arrays}, journal ={IEEE Transactions on Computers}, volume = {35}, number = {5}, issn = {0018-9340}, year = {1986}, pages = {431-440}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1986.1676785}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Study of Pipelining in Computing Arrays IS - 5 SN - 0018-9340 SP431 EP440 EPD - 431-440 A1 - H.V. Jagadish, A1 - R.G. Mathews, A1 - T. Kailath, A1 - J.A. Newkirk, PY - 1986 KW - systolic array KW - Pipelining VL - 35 JA - IEEE Transactions on Computers ER - | |||
In this paper, we take a hard look at scheduling considerations in computing arrays. A simple sufficient condition is developed for determining whether a computing array can be pipelined. If the array cannot be pipelined in the form given, the condition also indicates the direction in which to proceed to make it pipelineable. The overall framework and methodology take a good part of the load off the logical architect of the array, and make the translation from the logical to the physical architecture a mechanical process.
Index Terms:
systolic array, Pipelining
Citation:
H.V. Jagadish, R.G. Mathews, T. Kailath, J.A. Newkirk, "A Study of Pipelining in Computing Arrays," IEEE Transactions on Computers, vol. 35, no. 5, pp. 431-440, May 1986, doi:10.1109/TC.1986.1676785
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