Issue No.05 - May (1986 vol.35)
H.V. Jagadish , AT&T Bell Laboratories
In this paper, we take a hard look at scheduling considerations in computing arrays. A simple sufficient condition is developed for determining whether a computing array can be pipelined. If the array cannot be pipelined in the form given, the condition also indicates the direction in which to proceed to make it pipelineable. The overall framework and methodology take a good part of the load off the logical architect of the array, and make the translation from the logical to the physical architecture a mechanical process.
systolic array, Pipelining
R.G. Mathews, T. Kailath, H.V. Jagadish, "A Study of Pipelining in Computing Arrays", IEEE Transactions on Computers, vol.35, no. 5, pp. 431-440, May 1986, doi:10.1109/TC.1986.1676785