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April 1986 (vol. 35 no. 4)
pp. 379-383
| ASCII Text | x | ||
| S. Bozorgui-Nesbat, E.J. McCluskey, "Lower Overhead Design for Testability of Programmable Logic Arrays," IEEE Transactions on Computers, vol. 35, no. 4, pp. 379-383, April, 1986. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1986.1676775, author = {S. Bozorgui-Nesbat and E.J. McCluskey}, title = {Lower Overhead Design for Testability of Programmable Logic Arrays}, journal ={IEEE Transactions on Computers}, volume = {35}, number = {4}, issn = {0018-9340}, year = {1986}, pages = {379-383}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1986.1676775}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Lower Overhead Design for Testability of Programmable Logic Arrays IS - 4 SN - 0018-9340 SP379 EP383 EPD - 379-383 A1 - S. Bozorgui-Nesbat, A1 - E.J. McCluskey, PY - 1986 KW - test generation for PLA's KW - Design for testability KW - PLA testing KW - programmable logic arrays (PLA) VL - 35 JA - IEEE Transactions on Computers ER - | |||
A new technique for designing easily testable PLA's is presented. The salient features of this technique are: 1) low overhead, 2) high fault coverage, 3) simple design, and 4) little or no impact on normal operation of PLA's. This technique consists of the addition of input lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and device can be tested. Using this technique, all multiple stuck-at faults, as well as all multiple extra and multiple missing device faults, are detected.
Index Terms:
test generation for PLA's, Design for testability, PLA testing, programmable logic arrays (PLA)
Citation:
S. Bozorgui-Nesbat, E.J. McCluskey, "Lower Overhead Design for Testability of Programmable Logic Arrays," IEEE Transactions on Computers, vol. 35, no. 4, pp. 379-383, April 1986, doi:10.1109/TC.1986.1676775
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