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Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
April 1986 (vol. 35 no. 4)
pp. 375-379
M.S. Abadir, Department of Electrical Engineering?Systems, University of Southern California
This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.
Index Terms:
functional test generation, Binary decision diagrams, D algorithm, fault model, fault detection, functional faults
Citation:
M.S. Abadir, H.K. Reghbati, "Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams," IEEE Transactions on Computers, vol. 35, no. 4, pp. 375-379, April 1986, doi:10.1109/TC.1986.1676774
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