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Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
April 1986 (vol. 35 no. 4)
pp. 375-379
| ASCII Text | x | ||
| M.S. Abadir, H.K. Reghbati, "Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams," IEEE Transactions on Computers, vol. 35, no. 4, pp. 375-379, April, 1986. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1986.1676774, author = {M.S. Abadir and H.K. Reghbati}, title = {Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams}, journal ={IEEE Transactions on Computers}, volume = {35}, number = {4}, issn = {0018-9340}, year = {1986}, pages = {375-379}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1986.1676774}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams IS - 4 SN - 0018-9340 SP375 EP379 EPD - 375-379 A1 - M.S. Abadir, A1 - H.K. Reghbati, PY - 1986 KW - functional test generation KW - Binary decision diagrams KW - D algorithm KW - fault model KW - fault detection KW - functional faults VL - 35 JA - IEEE Transactions on Computers ER - | |||
This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.
Index Terms:
functional test generation, Binary decision diagrams, D algorithm, fault model, fault detection, functional faults
Citation:
M.S. Abadir, H.K. Reghbati, "Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams," IEEE Transactions on Computers, vol. 35, no. 4, pp. 375-379, April 1986, doi:10.1109/TC.1986.1676774
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