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Test Schedules for VLSI Circuits Having Built-In Test Hardware
April 1986 (vol. 35 no. 4)
pp. 361-367
M.S. Abadir, Department of Electrical Engineering, University of Southern Califomia
In this correspondence, the concept of a test schema which describes how a test methodology is to execute is introduced. We also introduce the powerful concept of an I path which is used to transfer data unchanged from one place in a circuit to another. The process of embedding a test schema into an actual circuit is described. This produces a test plan for the circuit which specifies the sequence of actions that need to be carried out to execute the test. A theory of test plan execution overlap is presented, and is used as the basis for constructing test schedules with optimal execution times.
Index Terms:
test schedules, Design for testability, pipelining, testable design methodology, testing, test plans
Citation:
M.S. Abadir, M.A. Breuer, "Test Schedules for VLSI Circuits Having Built-In Test Hardware," IEEE Transactions on Computers, vol. 35, no. 4, pp. 361-367, April 1986, doi:10.1109/TC.1986.1676771
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