Issue No.04 - April (1986 vol.35)
C.S. Raghavendra , Department of Electrical Engineering-Systems, University of Southern Califomia
In this paper, we study fault-tolerant multiprocessor systems employing redundant-path multistage interconnection networks. Such systems permit interprocessor communication in the presence of faulty components in the network. The interconnection network considered is a delta network augmented with an extra switching stage in front. When the first and last stages are fault-free, the extra-stage delta networks continue to provide full access in the presence of all single and many multiple faults in switching elements of the intermediate stages. In this paper, we use graph-theoretic techniques to study the problem of routing permutations in extra-stage delta networks when faults are present in the network. We first formulate the problem of performing an arbitrary permutation on the fault-free network as a vertex-coloring problem and later extend this to networks with noncritical faults. Although the general problem of realizing a permutation in the minimum number of passes is intractable, classes of permutations with some regularity can be routed optimally. To illustrate the idea, we consider the class of BPC (bit permute-complement) permutations: algorithms for performing arbitrary permutations in this class on the extra-stage delta network are given, both for the fault-free network and for a network with noncritical faults.
redundant-path interconnection, BPC permutations, delta networks, fault- tolerant routing, graph coloring, multiprocessor systems, multistage interconnection, omega network, permutation networks
C.S. Raghavendra, A. Varma, "Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks", IEEE Transactions on Computers, vol.35, no. 4, pp. 307-316, April 1986, doi:10.1109/TC.1986.1676763