Issue No.03 - March (1986 vol.35)
I.V. Ramakrishnan , Department of Computer Science, State University of New York
This paper presents a formal model of linear array processors suitable for VLSI implementation as well as graph representations of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model and the structure of correctly mappable graphs are examined. The formalism developed is used to synthesize algorithms for this model.
VLSI, Array processors, graphs, mapping, parallel processing, synthesis
D.S. Fussell, I.V. Ramakrishnan, "Mapping Homogeneous Graphs on Linear Arrays", IEEE Transactions on Computers, vol.35, no. 3, pp. 189-209, March 1986, doi:10.1109/TC.1986.1676744