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I. Koren, Department of Electrical Engineering, Technion?Israel Institute of Technology
The above paper1presents an approach to the design of fault- tolerant processor arrays. In Section IV of this paper (related work on fault-tolerant networks) the author criticizes a previously published approach presented by Koren [1] and by Gordon, Koren and Silberman [2]. In [1], an algorithm for structuring a linear array on a rectangular grid of processing elements (PE's), some of w
Citation:
I. Koren, "Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors"," IEEE Transactions on Computers, vol. 35, no. 1, pp. 93, Jan. 1986, doi:10.1109/TC.1986.1676668
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