Issue No.01 - January (1986 vol.35)
This correspondence concerns applications of optimization techniques based on global flow analysis to the automated design of logic. Previous optimization work on logic design has relied primarily on either local transformations on the circuit graph or on the use of two-level Boolean minimization. Our methods involve linear time algorithms which extend the scope of local optimizations to the entire design. Their use, in some cases, has resulted in a reduction in gate count, in improved control over path length, and in better detection and elimination of redundancy.
PLA's, Automatic logic design, compilers, control logic, global flow analysis
"Global Flow Analysis in Automatic Logic Design", IEEE Transactions on Computers, vol.35, no. 1, pp. 77-81, January 1986, doi:10.1109/TC.1986.1676664