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Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays
January 1986 (vol. 35 no. 1)
pp. 70-73
F. Ozguner, Department of Electrical Engineering, The Ohio State University
A method for the deductive fault simulation of faults in inverter-free circuits is presented. It is shown that in an inverter-free circuit, fault lists on lines with complementary logic values are disjoint, and fault list calculations can be done by performing fewer set operations compared to conventional gate level deductive simulation. Applications of the method to programmable logic arrays (PLA's) and deductive fault simulation of PLA faults are discussed.
Index Terms:
programmable logic arrays, Deductive simulation, fault simulation, inverter-free circuits
Citation:
F. Ozguner, "Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays," IEEE Transactions on Computers, vol. 35, no. 1, pp. 70-73, Jan. 1986, doi:10.1109/TC.1986.1676661
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