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A Heuristic for Suffix Solutions
January 1986 (vol. 35 no. 1)
pp. 34-42
A. Bilgory, Department of Electrical Engineering, Technion?Israel Institute of Technology
The suffix problem has appeared in solutions of recurrence systems for parallel and pipelined machines and more recently in the design of gate and silicon compilers. In this paper we present two algorithms. The first algorithm generates parallel suffix solutions with minimum cost for a given length, time delay, availability of initial values, and fanout. This algorithm generates a minimal solution for any length n and depth range from log2 n to n. The second algorithm reduces the size of the solutions generated by the first algorithm.
Index Terms:
VLSI layouts, Area-time complexity, binary addition, carry- lookhead computation, combinational logic, prefix computation, recurrence computation, silicon compilers
Citation:
A. Bilgory, D.D. Gajski, "A Heuristic for Suffix Solutions," IEEE Transactions on Computers, vol. 35, no. 1, pp. 34-42, Jan. 1986, doi:10.1109/TC.1986.1676655
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