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An Optimal Instruction-Scheduling Model for a Class of Vector Processors
November 1985 (vol. 34 no. 11)
pp. 981-995
S. Arya, Gould Research Center
An integer programming model that portrays the architectural features of a class of vector and array processors has been developed. This model is used to produce optimal schedules for low-level-instruction codes of such processors. Optimal schedules are produced for both straight codes and instruction loops. Loop scheduling is separately considered because of special consideration that must be given to the effects of the instructions of consecutive loop iterations on each other that are hidden when static instruction scheduling approach is used. Using the model, a number of experiments have been conducted in optimal scheduling of Cray assembly codes.
Index Terms:
vector processing, Computer architecture, instruction loop, integer programming, scheduling
S. Arya, "An Optimal Instruction-Scheduling Model for a Class of Vector Processors," IEEE Transactions on Computers, vol. 34, no. 11, pp. 981-995, Nov. 1985, doi:10.1109/TC.1985.1676531
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