|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
An Optimal Instruction-Scheduling Model for a Class of Vector Processors
November 1985 (vol. 34 no. 11)
pp. 981-995
| ASCII Text | x | ||
| S. Arya, "An Optimal Instruction-Scheduling Model for a Class of Vector Processors," IEEE Transactions on Computers, vol. 34, no. 11, pp. 981-995, November, 1985. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1985.1676531, author = {S. Arya}, title = {An Optimal Instruction-Scheduling Model for a Class of Vector Processors}, journal ={IEEE Transactions on Computers}, volume = {34}, number = {11}, issn = {0018-9340}, year = {1985}, pages = {981-995}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1985.1676531}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - An Optimal Instruction-Scheduling Model for a Class of Vector Processors IS - 11 SN - 0018-9340 SP981 EP995 EPD - 981-995 A1 - S. Arya, PY - 1985 KW - vector processing KW - Computer architecture KW - instruction loop KW - integer programming KW - scheduling VL - 34 JA - IEEE Transactions on Computers ER - | |||
An integer programming model that portrays the architectural features of a class of vector and array processors has been developed. This model is used to produce optimal schedules for low-level-instruction codes of such processors. Optimal schedules are produced for both straight codes and instruction loops. Loop scheduling is separately considered because of special consideration that must be given to the effects of the instructions of consecutive loop iterations on each other that are hidden when static instruction scheduling approach is used. Using the model, a number of experiments have been conducted in optimal scheduling of Cray assembly codes.
Index Terms:
vector processing, Computer architecture, instruction loop, integer programming, scheduling
Citation:
S. Arya, "An Optimal Instruction-Scheduling Model for a Class of Vector Processors," IEEE Transactions on Computers, vol. 34, no. 11, pp. 981-995, Nov. 1985, doi:10.1109/TC.1985.1676531
Usage of this product signifies your acceptance of the Terms of Use.

