Issue No.10 - Oct. (1985 vol.34)
Trevor N. Mudge , Computing Research Lab, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109
Humoud B. Al-Sadoun , Department of Electrical Engineering, Kuwait University, P.O. Box 5969, Kuwait
This paper presents a discrete time model of memory interference in multiprocessor systems employing multiple-bus interconnection networks. It differs from earlier models in its ability to model variable connection time and arbitrary inter-request time. The model describes each processing element's behavior by means of a semi-Markov process. It takes as input the number of processing elements, the number of memory modules, the number of buses, the mean think time of the processing elements, and the first and second moments of the connection time between processing elements and memories. The model produces as output the memory bandwidth, processing element utilization, memory module utilization, average queue length at a memory, and average waiting time experienced by a processing element while waiting to access a memory. Using the model, it is possible to analyze the interaction of the input parameters on the system performance. This modeling capability is attained without having to employ a complex Markov chain. In fact, a four-state semi-Markov process is sufficient regardless of the think and connection time distributions. The accuracy and capability of the model is illustrated.
semi-Markov processes, Markov chains, memory bandwidth, memory interference, multiple-bus system, multiprocessors, performance evaluation
Trevor N. Mudge, Humoud B. Al-Sadoun, "A semi-Markov model for the performance of multiple-bus systems", IEEE Transactions on Computers, vol.34, no. 10, pp. 934-942, Oct. 1985, doi:10.1109/TC.1985.6312197