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Oct. 1985 (vol. 34 no. 10)
pp. 918-926
Chita R. Das, Center for Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, LA 70504
Laxmi N. Bhuyan, Center for Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, LA 70504
Multiprocessor systems should be designed considering both performance and reliability issues. They should support graceful degradation by isolating the failed components and by reconfiguring to a new state with decreased performance. We present in this paper the effect of failures on the performance of multiple-bus multiprocessors. Bandwidth expressions for this architecture are derived for uniform and nonuniform memory references. Mathematical models are developed to compute the reliability and the performance related bandwidth availability (BA). The results obtained for the multiple-bus interconnection are compared with those of a crossbar. The models are also extended to analyze the partial bus structure where the memories are divided into groups and each group is connected to a subset of buses. The reliability and the BA of the multiple-bus and partial-bus architectures are compared.
Index Terms:
reliability,Bandwidth availability,crossbar,graceful degradation,multiple bus,multiprocessor,partial bus,performance analysis
Citation:
Chita R. Das, Laxmi N. Bhuyan, "Bandwidth availability of multiple-bus multiprocessors," IEEE Transactions on Computers, vol. 34, no. 10, pp. 918-926, Oct. 1985, doi:10.1109/TC.1985.6312195
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