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Oct. 1985 (vol. 34 no. 10)
pp. 874-880
| ASCII Text | x | ||
| Daniel A. Reed, "Iterative solution of large, sparse linear systems on a static data flow architecture: Performance studies," IEEE Transactions on Computers, vol. 34, no. 10, pp. 874-880, Oct., 1985. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1985.6312190, author = {Daniel A. Reed}, title = {Iterative solution of large, sparse linear systems on a static data flow architecture: Performance studies}, journal ={IEEE Transactions on Computers}, volume = {34}, number = {10}, issn = {0018-9340}, year = {1985}, pages = {874-880}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1985.6312190}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Iterative solution of large, sparse linear systems on a static data flow architecture: Performance studies IS - 10 SN - 0018-9340 SP874 EP880 EPD - 874-880 A1 - Daniel A. Reed, PY - 1985 KW - sparse linear systems KW - Algorithm analysis KW - data flow KW - parallel algorithms KW - performance models VL - 34 JA - IEEE Transactions on Computers ER - | |||
The applicability of static data flow architectures to the iterative solution of sparse linear systems of equations is investigated. An analytic performance model of a static data flow computation is developed. This model includes both spatial parallelism, concurrent execution in multiple PE's, and pipelining, the streaming of data from array memories through the PE's. The performance model is used to analyze a row partitioned iterative algorithm for solving sparse linear systems of algebraic equations. Based on this analysis, design parameters for the static data flow architecture as a function of matrix sparsity and dimension are proposed.
Index Terms:
sparse linear systems,Algorithm analysis,data flow,parallel algorithms,performance models
Citation:
Daniel A. Reed, "Iterative solution of large, sparse linear systems on a static data flow architecture: Performance studies," IEEE Transactions on Computers, vol. 34, no. 10, pp. 874-880, Oct. 1985, doi:10.1109/TC.1985.6312190
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