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HighSpeed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
September 1985 (vol. 34 no. 9)
pp. 789796
ASCII Text  x  
N. Takagi, H. Yasuura, S. Yajima, "HighSpeed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree," IEEE Transactions on Computers, vol. 34, no. 9, pp. 789796, September, 1985.  
BibTex  x  
@article{ 10.1109/TC.1985.1676634, author = {N. Takagi and H. Yasuura and S. Yajima}, title = {HighSpeed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree}, journal ={IEEE Transactions on Computers}, volume = {34}, number = {9}, issn = {00189340}, year = {1985}, pages = {789796}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1985.1676634}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  HighSpeed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree IS  9 SN  00189340 SP789 EP796 EPD  789796 A1  N. Takagi, A1  H. Yasuura, A1  S. Yajima, PY  1985 KW  VLSI KW  Arithmetic operations KW  binary integer multiplication KW  carrypropagationfree adder KW  hardware algorithm KW  highspeed multiplier KW  redundant binary representation KW  signeddigit number representation VL  34 JA  IEEE Transactions on Computers ER   
A highspeed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two ndigit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our twotoone conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.
Index Terms:
VLSI, Arithmetic operations, binary integer multiplication, carrypropagationfree adder, hardware algorithm, highspeed multiplier, redundant binary representation, signeddigit number representation
Citation:
N. Takagi, H. Yasuura, S. Yajima, "HighSpeed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree," IEEE Transactions on Computers, vol. 34, no. 9, pp. 789796, Sept. 1985, doi:10.1109/TC.1985.1676634
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