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Issue No.08 - August (1985 vol.34)
pp: 741-744
R. Gnanasekaran , Department of Electrical Engineering and Computer Science, University of Nevada
ABSTRACT
A fast serial-parallel (FSP) multiplier design is derived from the carry-save add-shift (CSAS) multiplier structure. The CSAS technique accepts multiplier bits serially (lsb first) and produces outputs serially (lsb first). Multiplication of two n bit unsigned numbers requires 2n clock cycles to complete the process out of which n clocks are used for n-row carry-save additions, and the other n clocks are utilized only to propagate the remaining carries. This CSAS structure is modified so that it operates as a CSAS unit for the first n clocks and reconfigures itself as an n bit ripple-carry parallel adder at the (n + 1)st clock, thus allowing the carries to ripple through, eliminating the delay due to storage elements during the last n clocks. It is shown that this modification results in an about one-third increase in speed for an approximately one-third increase in hardware. The technique is extended to signed numbers represented in 2's complement form. Also, it is shown how these implementations can be modularized.
INDEX TERMS
2's complement multiplication, Add-shift multiplier, array multiplier, carry-save addition, pipeline multiplier, ripple-carry parallel adder, serial-parallel multiplier
CITATION
R. Gnanasekaran, "A Fast Serial-Parallel Binary Multiplier", IEEE Transactions on Computers, vol.34, no. 8, pp. 741-744, August 1985, doi:10.1109/TC.1985.1676620
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