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Square-Rooting Algorithms for High-Speed Digital Circuits
August 1985 (vol. 34 no. 8)
pp. 724-733
S. Majerski, Instytut Maszyn Matematycznych
Two binary algorithms for the square rooting of a number or of a sum of two numbers are presented. They are based on the classical nonrestoring method. The main difference lies in the replacement of subtractions and additions by a parallel reduction f three summands, which may be positive and negative, to two summands to eliminate the carry propagation. Two of three summands form the successive partial remainder. Their most significant bit triples, sometimes together with a sign bit of the earlier partial remainder, are used to determine digits -1,0, +1 of a redundant square-root notation. These digits are transformed during the square-rooting process into the conventional notation square-root bits which are next used in further square-rooting steps to form the third reduced summands.
Index Terms:
redundant number notation, Binary square rooting, carry-propagation elimination, parallel reduction of summands
Citation:
S. Majerski, "Square-Rooting Algorithms for High-Speed Digital Circuits," IEEE Transactions on Computers, vol. 34, no. 8, pp. 724-733, Aug. 1985, doi:10.1109/TC.1985.1676618
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