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VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
August 1985 (vol. 34 no. 8)
pp. 709-717
C.C. Wang, Communications Systems Research, Jet Propulsion Laboratory, California Institute of Technology
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura [1] recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.
Index Terms:
systolic array, Finite field inverse, finite field multiplication, finite field multiplier, inverse, Massey-Omura multiplier, normal basis, normal basis multiplier, pipeline
Citation:
C.C. Wang, T.K. Troung, H.M. Shao, L.J. Deutsch, J.K. Omura, I.S. Reed, "VLSI Architectures for Computing Multiplications and Inverses in GF(2m)," IEEE Transactions on Computers, vol. 34, no. 8, pp. 709-717, Aug. 1985, doi:10.1109/TC.1985.1676616
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