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July 1985 (vol. 34 no. 7)
pp. 652-658
H.-W. Lang, Institut f?r Informatik und Praktische Mathematik, Christian-Albrechts-Universit?t Kiel
A parallel algorithm for sorting n data items in O(n) steps is presented. Its simple structure and the fact that it needs local communication only make it suitable for an implementation in VLSI technology. The algorithm is based on a merge algorithm that merges four subfiles stored in a mesh-connected processor array. This merge algorithm is composed of the perfect shuffle and odd-even-transposition sort. For the VLSI implementation a systolic version of the algorithm is presented. The area and time complexities for a bit-serial and a bit-parallel version of this implementation are analyzed.
Index Terms:
VLSI complexity, Odd-even-transposition sort, mesh-connected processor array, perfect shuffle, sorting, systolic array, VLSI algorithms
Citation:
H.-W. Lang, M. Schimmler, H. Schmeck, H. Schroder, "Systolic Sorting on a Mesh-Connected Network," IEEE Transactions on Computers, vol. 34, no. 7, pp. 652-658, July 1985, doi:10.1109/TC.1985.1676603
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