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Integrated-Circuit Logarithmic Arithmetic Units
May 1985 (vol. 34 no. 5)
pp. 475-483
J.H. Lang, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
This correspondence examines integrated-circuit logarithmic arithmetic units which include adders, subtracters, multipliers, and dividers. The design of these arithmetic units is reviewed, and an example arithmetic unit which performs multiplication followed by addition is designed in detail. The design results are used to develop a size and speed comparison of integrated-circuit logarithmic and fixed-point arithmetic units. This comparison is exercised through a video signal processing example. It is concluded from this comparison that logarithmic arithmetic units are smaller than, and as fast as, fixed-point arithmetic units with comparable capabilities in digital signal processing applications characterized by large dynamic range and moderate computational accuracy requirements. Further, this comparison quantitatively illustrates the interaction of digital-signal-processing and integrated-circuit issues in the design of special-purpose digital signal processors.
Index Terms:
VLSI, Arithmetic unit comparisons, logarithmic arithmetic, multiplier-accumulators, special-purpose digital signal processors
J.H. Lang, C.A. Zukowski, R.O. Lamaire, null Chae Han, "Integrated-Circuit Logarithmic Arithmetic Units," IEEE Transactions on Computers, vol. 34, no. 5, pp. 475-483, May 1985, doi:10.1109/TC.1985.1676588
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