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On the Performance of Synchronous Multiprocessors
May 1985 (vol. 34 no. 5)
pp. 462-466
null Hung-Chang Du, Department of Computer Science, University of Minnesota
In this correspondence, we study the performance of a multiprocessor in which a crossbar is employed to interconnect p processors to m commonly shared memory modules. A set of nonuniformly distributed probabilities including a probability P(0) which denotes the probability of a processor not generating any request is also employed to illustrate the program behavior, but no distinction is made between processors. Several relations between the average request completion time, the average processor utilization, and the effective memory bandwidth are obtained. One approximation method based on the idea of aggregation is proposed. Its solutions are compared to the exact solution.
Index Terms:
queueing model, Crossbar switch, memory interference, MIMD architectures, multiprocessor systems
null Hung-Chang Du, "On the Performance of Synchronous Multiprocessors," IEEE Transactions on Computers, vol. 34, no. 5, pp. 462-466, May 1985, doi:10.1109/TC.1985.1676585
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