This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Dynamically Restructurable Fault-Tolerant Processor Network Architectures
May 1985 (vol. 34 no. 5)
pp. 434-447
D.K. Pradhan, Departnment of Electrical and Computer Engineering, University of Massachusetts
A class of novel fault-tolerant multiprocessor networks is proposed. These networks are restructurable in that they can assume different logical configurations to suit different problem environments. More importantly, this restructuriing capability is not altered even after the occurrence of faults. These networks are novel in that they uniquely combine certain desirable features, including self-routing of messages, dynamic reconfigurability, fault-tolerance, the ability to incorporate incremental extension, as well as the capacity to be partitioned with fault-tolerance. What is important about these fault-tolerant features is that they are built-in as an integral part of the design, and not as done traditionally, by means of redundancy.
Index Terms:
self-routing, Binary tree, circuit switching, distributed system, dynamic processing, emulation, faplt-tolerance, fault-tolerant interconnection, linear array, nmodular network, packet switching, parallel system, processor array
Citation:
D.K. Pradhan, "Dynamically Restructurable Fault-Tolerant Processor Network Architectures," IEEE Transactions on Computers, vol. 34, no. 5, pp. 434-447, May 1985, doi:10.1109/TC.1985.1676583
Usage of this product signifies your acceptance of the Terms of Use.